1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a multi-chip package system including a plurality of semiconductor chips.
2. Description of the Related Art
In general, semiconductor devices including Double Data Rate Synchronous DRAM (DDR SDRAM) have developed in various directions to satisfy users' requests. The development directions may include a package technology. A multi-chip package has been recently proposed as a package technology for a semiconductor device. The multi-chip package includes a plurality of semiconductor chips constructing a single chip, and a plurality of memory chips with a memory function may be used to increase a memory capacity, or a plurality of memory chips with different functions may be used to improve desired performance. For reference, the multi-chip package may be divided into a single-layer multi-chip package and a multilayer multi-chip package depending on configurations. The single-layer multi-chip package includes a plurality of semiconductor chips arranged in parallel to each other on the same plane, for example, coplanar, and the multi-chip package includes a plurality of semiconductor chips stacked therein.
FIG. 1 is a block diagram for explaining a conventional chip package.
Referring to FIG. 1, the multi-chip package includes a plurality of semiconductor chips 110 and a controller 120 to control the semiconductor chips 110. The plurality of semiconductor chips 110 and the controller 120 are connected to each other through a signal transmission line LL, and the controller 120 transmits a predetermined signal through the signal transmission line LL so as to control the plurality of semiconductor chips 110.
Meanwhile, recent semiconductor devices have been developed in such a direction as to store a larger amount of data and perform various operations at higher speed. Therefore, the number of semiconductor chips 110 constructing a multi-chip package as described above has been gradually increased. When the number of semiconductor chips 110 is increased, it may mean that loading of the signal transmission line LL connected to the controller 120 is increased as much. Furthermore, when the loading of the signal transmission line LL is increased, it may mean that a delay amount corresponding to the increased loading is additionally reflected into a signal transmitted through the signal transmission line LL. When the delay amount is significantly increased, the signal may not be transmitted at high speed.